1. Field of the Invention
The present invention relates to a one-chip clock synchronized memory device having a memory with a built-in logic analyzer function capable of accurately analyzing operations of a memory inside a system in operation.
2. Background Art
A presumably failed clock synchronized memory device of the above type held in systems has been analyzed by a logic analyzer for operation, with probes attached to the memory pins for control signals, address signals and data signals. The timings of these signals are observed so that suspected signals may be detected by the logic analyzer. A minimum of 30 to 40 probes would be needed optimally to carry out such verifications, except that functional and physical constraints of the logic analyzer often limit the number of probes to less than 20. The 10-odd probes thus selected are used conventionally to check and analyze the signals of the memory in question.
Recently introduced systems, for example, personal computers (PC), are noted for their complicated functionality, combined with a large-scale memory. Such as a 168-pin module memory. To analyze operations of such a memory accurately would require setting up nearly 160 probes for attachment to memory pins. In cases where two 168-pin modules are installed in a system, the need has been recognized to prepare as many as 320 pins for analyzing operations of the incorporated memories. That need is acutely felt during attempts to analyze a failure that is detectable only when an application program is run on the system.
As outlined above, memory failures in systems are analyzed conventionally by the logic analyzer with probes attached to memory pins. However, setting up a large number of probes needed for the check has often turned out to be impractical, as well as costly.
Furthermore, there has been a growing need to efficiently and accurately analyze for the failure of systems containing clock synchronized memory chips that are higher in operating speed and more complex than ever in structure.